Semiconductor memory device comprising memory cells with floating gate electrode and method of production

US7250651B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Karl-Heinz Kusters · Krefeld, DE
• Josef Willer · Riemerling, DE
• Corvin Liaw · Birkenfeld, DE

Key dates

• Filing date: Aug 19, 2004
• Grant date: Jul 31, 2007
• Expiry date: Aug 19, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/68

Abstract

Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.