Method for projection of a circuit pattern, which is arranged on a mask, onto a semiconductor wafer
US7252913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A simulation is carried out of a projection based on an electronically stored circuit pattern and adjustable projection parameters and optical parameters which characterize the specific characteristics of a projection apparatus. Positions at which it is predicted that side lobes will occur in the event of an actual projection are identified in the calculated circuit pattern. The positions of the side lobes are transmitted to a manufacturing unit and are recorded in a measurement program. A wafer, which has been exposed by a mask, is inspected for side lobes, at least at precisely those transmitted positions using the measurement program. The adjustable projection parameters are adapted, a radiation-sensitive layer is removed from and reapplied to the wafer and the projection is repeated with the adapted projection parameters depending on the detection result. The control process is repeated until the side lobes have been completely prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.