Method for fabricating interconnection in an insulating layer on a wafer
US7253093B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Nov 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76892
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.