Method of extracting properties of back end of line (BEOL) chip architecture
US7260810B2 · kind B2 · utility
8Cited by
9References
32Claims
0Family size
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Key dates
| Filing date | Oct 16, 2003 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Sep 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/23
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.