Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor
US7262109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Aug 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.