Integrated semiconduct memory with test circuit

US7266027B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ralf Schneider · Birkenfeld, DE
• Stephan Schröder · Birkenfeld, DE
• Manfred Proll · Dorfen, DE
• Herbert Benzinger · Birkenfeld, DE

Key dates

• Filing date: Sep 27, 2005
• Grant date: Sep 4, 2007
• Expiry date: Feb 1, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/1202
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.