Patent · US Expired

Multi-bit virtual-ground NAND memory device

US7272040B2 · kind B2 · utility

4Cited by

11References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Mikolajick · Birkenfeld, DE
Josef Willer · Riemerling, DE
Corvin Liaw · Birkenfeld, DE

Key dates

Filing date	Apr 29, 2005
Grant date	Sep 18, 2007
Priority date	—
Expiry date	Apr 29, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH10B69/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.