Delay circuit with reset-based forward path static delay
US7276947B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2006 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Jul 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.