System and method for forming an integrated barrier layer
US7279432B2 · kind B2 · utility
41Cited by
64References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 15, 2003 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for forming an integrated barrier layer on a substrate is described. The integrated barrier layer comprises at least a first refractory metal layer and a second refractory metal layer. The integrated barrier layer is formed using a dual-mode deposition process comprising a chemical vapor deposition (CVD) step and a cyclical deposition step. The dual-mode deposition process may be performed in a single process chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.