Integrated memory device and method for operating the same

US7280392B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Corvin Liaw · Birkenfeld, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Jan 26, 2006
• Grant date: Oct 9, 2007
• Expiry date: Jan 26, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2213/77
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines. A checking unit determines whether to invert data values to be stored in memory cells coupled to at least a section of respective ones of the first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values in order to reduce the number memory cells programmed in the low-resistance state and the resulting leakage current.