Dual wired integrated circuit chips
US7285477B1 · kind B1 · utility
24Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2006 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | May 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.