Asynchronous-mode sync FIFO having automatic lookahead and deterministic tester operation
US7287105B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2005 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | May 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer control logic configured for reading a selected number of the buffer entries based on a detected number of receive clock edges within one local clock cycle. Valid data is identified based on the number of clock edges exceeding a selected threshold. A selected pointer offset is obtained from a lookahead table, specifying multiple pointer offsets for accommodating latency encountered at respective prescribed available frequencies, based on matching the determined frequency to one of the prescribed available frequencies. The selected pointer offset is added to a read pointer to offset the latency encountered from edge detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.