Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure
US7288487B1 · kind B1 · utility
4Cited by
11References
18Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 1, 2004 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | May 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for eliminating and/or mitigating bridging and/or leakage caused by the contamination of a dielectric layer with fragments and/or residues of a conductive material are disclosed. The methods involve exposing a semiconductor substrate with a dielectric layer contaminated with fragments and/or residues of conductive materials to one or more conductor and/or dielectric etches. The disclosure by eliminating and/or mitigating metal bridging and/or leakage can provide one or more of the following advantages: high device reliability, decreased manufacturing cost, more efficient metallization, and increased performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.