Methods of fabricating semiconductor devices having a dual stress liner
US7297584B2 · kind B2 · utility
17Cited by
2References
12Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 7, 2005 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Nov 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.