Stacked integrated circuit package-in-package system with recessed spacer
US7298037B2 · kind B2 · utility
21Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2006 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Feb 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a substrate with the recess positioned therebetween, and attaching a first electrical interconnect extending from the recess and connected between the integrated circuit die and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.