Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
US7301835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Oct 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.