Critical dimension control in a semiconductor fabrication process
US7306746B2 · kind B2 · utility
5Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Oct 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for controlling a critical dimension in an etched structure comprises the steps of: forming a hard mask above a substrate, measuring a critical dimension of the hard mask, and using the measured hard mask critical dimension to control a critical dimension trim operation performed on a circuit trace above the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.