Delay locked loop circuitry for clock delay adjustment
US7308065B2 · kind B2 · utility
9Cited by
40References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2006 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Apr 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.