Memory device having a nanocrystal charge storage region and method
US7309650B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Jan 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.