Copper plating of semiconductor devices using single intermediate low power immersion step
US7312149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2004 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Jan 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2885
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.