Stacked integrated circuit package-in-package system
US7312519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2006 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first top molding compound to cover the first electrical interconnects and a portion of the top side of the first substrate, and encapsulating a first bottom molding compound to cover the first integrated circuit and a bottom side the first substrate, and stacking a second device, having a second integrated circuit package, below the first device with a second top molding compound of the second device providing a space between the first device and the second device, wherein the second device includes the second top molding compound and a second bottom molding compound in a similar manner to the first device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.