Test apparatus and test method for testing a device under test
US7313496B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Apr 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2882
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.