Resistive memory device with a treated interface
US7326979B2 · kind B2 · utility
37Cited by
10References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 19, 2003 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Oct 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.