Technique for providing multiple stress sources in NMOS and PMOS transistors

US7329571B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Jan Hoentschel · Dresden, DE
• Andy Wei · Queensbury, US
• Manfred Horstmann · Dresden, DE
• Thorsten Kammler · Radeberg, DE

Key dates

• Filing date: Aug 24, 2006
• Grant date: Feb 12, 2008
• Expiry date: Aug 24, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.