Integration of fault detection with run-to-run control
US7337019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2002 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Sep 5, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Semiconductor wafers are processed in conjunction with a manufacturing execution system using a run-to-run controller and a fault detection system. A recipe is received from the manufacturing execution system by the run-to-run controller for controlling a tool. The recipe includes a setpoint for obtaining one or more target wafer properties. Processing of the wafers is monitored by measuring processing attributes including fault conditions and wafer properties using the fault detection system and one or more sensors. Setpoints of the recipe may be modified at the run-to-run controller according to the processing attributes to maintain the target wafer properties, except in cases when a fault condition is detected by the fault detection system. Thus, data acquired in the presence of tool or wafer fault conditions are not used for feedback purposes. In addition, fault detection models may be used to define a range of conditions indicative of a fault condition. In these cases, the fault detection models may be modified to incorporate, as parameters, setpoints of a recipe modified by a run-to-run controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.