Method for determining wordline critical dimension in a memory array and related structure
US7339222B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2006 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Jul 8, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/905
Abstract
According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.