Dual-gate integrated circuit semiconductor device
US7339240B2 · kind B2 · utility
1Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2006 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Feb 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.