Daisy chainable memory chip
US7342816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Aug 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip respondent to the address/command word. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. Read data is read from the array or is received from a second data bus port for subsequent re-driving on the first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.