Mark O. Maxson
78Patents
8h-index
35Co-inventors
74Inventor score
Filing activity: Mar 27, 2003 → Aug 29, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7342816B2 | Daisy chainable memory chip | Physics | 17 | Active |
| US7952478B2 | Capacitance-based microchip exploitation detection | Electricity | 17 | Active |
| US7884625B2 | Capacitance structures for defeating microchip tampering | Electricity | 14 | Active |
| US7074050B1 | Socket assembly with incorporated memory structure | Electricity | 14 | Expired |
| US7838336B2 | Method and structure for dispensing chip underfill through an opening in the chip | Electricity | 9 | Active |
| US7345900B2 | Daisy chained memory system | Physics | 9 | Active |
| US7088200B2 | Method and structure to control common mode impedance in fan-out regions | Electricity | 8 | Expired |
| US7050871B2 | Method and apparatus for implementing silicon wafer chip carrier passive devices | Physics | 8 | Expired |
| US7345901B2 | Computer system having daisy chained self timed memory chips | Physics | 7 | Active |
| US7234017B2 | Computer system architecture for a processor connected to a high speed bus transceiver | Physics | 7 | Expired |
| US9003559B2 | Continuity check monitoring for microchip exploitation detection | Physics | 6 | Active |
| US9341670B2 | Residual material detection in backdrilled stubs | Emerging Cross-Sectional Technologies | 6 | Active |
| US6757175B1 | Method and embedded bus bar structure for implementing power distribution | Emerging Cross-Sectional Technologies | 6 | Expired |
| US7701244B2 | False connection for defeating microchip exploitation | Electricity | 6 | Active |
| US8079134B2 | Method of enhancing on-chip inductance structure utilizing silicon through via technology | Emerging Cross-Sectional Technologies | 5 | Active |
| US7480201B2 | Daisy chainable memory chip | Physics | 5 | Active |
| US9438606B1 | Environmental-based location monitoring | Electricity | 5 | Active |
| US7036710B1 | Method and structures for implementing impedance-controlled coupled noise suppressor for differential interface solder column array | Electricity | 4 | Expired |
| US7202685B1 | Embedded probe-enabling socket with integral probe structures | Physics | 4 | Expired |
| US7667487B2 | Techniques for providing switchable decoupling capacitors for an integrated circuit | Physics | 4 | Active |
| US10318462B2 | Secure crypto module including optical glass security layer | Electricity | 4 | Active |
| US7675164B2 | Method and structure for connecting, stacking, and cooling chips on a flexible carrier | Electricity | 4 | Active |
| US9488690B2 | Residual material detection in backdrilled stubs | Emerging Cross-Sectional Technologies | 4 | Active |
| US7673093B2 | Computer system having daisy chained memory chips | Physics | 4 | Active |
| US8108647B2 | Digital data architecture employing redundant links in a daisy chain of component modules | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.