Integrated circuit having a top side wafer contact and a method of manufacture therefor
US7345343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2005 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Aug 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.