Computer system having daisy chained self timed memory chips
US7345901B2 · kind B2 · utility
7Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2006 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Aug 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.