System and method for CPI load balancing in SMT processors
US7353517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2003 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | May 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.