Method and apparatus for testing a memory device in quasi-operating conditions
US7356742B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 18, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Dec 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chipset LSI (large scale integrated circuit) on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.