Bottom conductor for integrated MRAM
US7358100B2 · kind B2 · utility
5Cited by
10References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 14, 2007 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Aug 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
Abstract
A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.