Patent · US Active

Trench isolation structure for a semiconductor device with reduced sidewall stress and a method of manufacturing the same

US7358150B2 · kind B2 · utility

3Cited by

3References

18Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Klaus Hempel · Dresden, DE
Stephan Kruegel · Sankt Goar, DE
Ekkehard Pruefer · Dresden, DE

Key dates

Filing date	Sep 19, 2006
Grant date	Apr 15, 2008
Priority date	—
Expiry date	Sep 19, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76237
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

By forming a non-oxidizable liner in isolation trenches, the creation of compressive stress may be significantly reduced, wherein, in illustrative embodiments, silicon nitride may be used as liner material. For this purpose, the etch behavior of the silicon nitride may be efficiently modified on the basis of an appropriate surface treatment, thereby providing a high degree of material integrity during a subsequent etch process for removing non-modified portions of silicon nitride, which may also be used as an efficient CMP stop layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.