Bi-directional read/program non-volatile floating gate memory array, and method of formation
US7358559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Feb 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6894
Abstract
A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.