Test parallelism increase by tester controllable switching of chip select groups
US7362632B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2006 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Oct 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.