Patent · US Expired

Method and circuit arrangement for resetting an integrated circuit

US7363561B2 · kind B2 · utility

3Cited by

2References

14Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Stefan Dietrich · Potsdam, DE
Thomas Hein · Hersbruck, DE
Patrick Heyne · Hersbruck, DE
Peter Schrogmeier · Hersbruck, DE

Key dates

Filing date	Apr 29, 2005
Grant date	Apr 22, 2008
Priority date	—
Expiry date	Jan 14, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1534
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.