Semiconductor memory having charge trapping memory cells and fabrication method thereof

US7365382B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Josef Willer · Riemerling, DE
• Thomas Mikolajick · Birkenfeld, DE
• Christoph Ludwig · Radeberg, DE
• Norbert Schulze · Radebeul, DE
• Karl-Heinz Kuesters · Munich, DE

Key dates

• Filing date: Feb 28, 2005
• Grant date: Apr 29, 2008
• Expiry date: Feb 28, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/691

Abstract

A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.