Measuring phase errors on phase shift masks
US7368208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jul 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70675
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Methods and apparatus for producing a semiconductor. A production reticle having a pattern that includes circuit features, phase shift target structures and overlay target structures is provided. The pattern is transferred multiple times across a test wafer surface for various focus levels to form a focus matrix. The pattern shift of the phase shift target structures is measured using an overlay metrology tool. The phase difference is calculated for each phase shift target structure, based on the pattern shift and the phase shift target structure focus level to qualify the phase difference of the production reticle. The pattern is transferred onto a production wafer when the phase difference meets desired limits. The pattern shift of the overlay target structures transferred to the production wafer is measured using an overlay metrology tool. The pattern placement error of the overlay target structures is calculated and the pattern placement error is qualified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.