Method and apparatus of stress relief in semiconductor structures

US7368804B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Mark Hoinkis · Fishkill, US
• Matthias Hierlemann · Fishkill, US
• Gerald Friese · Munich, DE
• Andy Cowley · Wappingers Falls, US
• Dennis J. Warner · Mechanicsville, US
• Erdem Kaltalioglu · Newburgh, US

Key dates

• Filing date: May 16, 2003
• Grant date: May 6, 2008
• Expiry date: May 6, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/12044
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.