System and method for high frequency stall design
US7370176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Dec 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.