Stacked mass storage flash memory package
US7375419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Sep 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The stacked multiple offset chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.