Patent · US Active

Programmable logic device architecture with multiple slice types

US7378872B1 · kind B1 · utility

0Cited by

3References

17Claims

0Family size

Assignee

Lattice Semiconductor Corporation · US

Inventors

Om P. Agrawal · Los Altos, US
Barry Britton · Orefield, US
Xiaojie He · Austin, US
Sajitha Wijesuriya · Macungie, US
Ming H. Ding · San Jose, US
Jun Zhao · Mianyang, CN

Key dates

Filing date	Jun 2, 2006
Grant date	May 27, 2008
Priority date	—
Expiry date	Jul 20, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17728
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.