Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process

US7381622B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Andreas Hellmich · Dresden, DE
• Gunter Grasshoff · Radebeul, DE
• Fernando Luiz Koch · Bitterfeld-Wolfen, DE
• Andy Wei · Queensbury, US
• Thorsten Kammler · Radeberg, DE

Key dates

• Filing date: Nov 14, 2006
• Grant date: Jun 3, 2008
• Expiry date: Jan 16, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.