System architecture and method for three-dimensional memory
US7383476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Jan 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.