Dual slice architectures for programmable logic devices
US7385417B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2006 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Jul 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.