Delay locked loop and method for setting a delay chain

US7391245B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Patrick Heyne · Hersbruck, DE
• Aaron Nygren · Birkenfeld, DE

Key dates

• Filing date: May 22, 2006
• Grant date: Jun 24, 2008
• Expiry date: Jul 26, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K2005/00058
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via the delay chain depending on the number of delay cells in the series that are activated for delay. The phase detector arrangement detects the phase of the signal at the output of each delay cell in the delay chain. The control unit activates a number Z of the delay cells of the delay chain based on the difference in phase of the original signal and the delayed signal.