Fabrication system and fabrication method
US7392106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Dec 30, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/908
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.