Patent · US Active

Polycarbosilane buried etch stops in interconnect structures

US7396758B2 · kind B2 · utility

3Cited by
6References
1Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 3, 2007
Grant dateJul 8, 2008
Priority date
Expiry dateJan 3, 2027

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10S438/97
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.